--
-- VHDL Architecture Balance.volume.arch
--
-- Created:
--          by - patli862.student (southfork-10.edu.isy.liu.se)
--          at - 13:49:58 09/29/11
--
-- using Mentor Graphics HDL Designer(TM) 2008.1 (Build 17)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY volume IS
   PORT( 
      fpga_clk          : IN     std_logic;
      Audio_in_right_v  : IN     std_logic_vector (23 DOWNTO 0);
      Audio_in_left_v   : IN     std_logic_vector (23 DOWNTO 0);
      Audio_out_right_v : OUT    std_logic_vector (23 DOWNTO 0);
      Audio_out_left_v  : OUT    std_logic_vector (23 DOWNTO 0);
      volume            : IN     std_logic_vector (1 DOWNTO 0);
      volume_to_vga     : OUT    std_logic_vector (3 DOWNTO 0)
   );

-- Declarations

END volume ;

--
ARCHITECTURE arch OF volume IS
SIGNAL volume_buff : std_logic_vector(3 DOWNTO 0);
SIGNAL aud_reg_right : std_logic_vector(23 DOWNTO 0);
SIGNAL aud_reg_left : std_logic_vector(23 DOWNTO 0);
BEGIN
  

PROCESS(fpga_clk)
  BEGIN
    if rising_edge(clk) then
    CASE volume_buff IS
    WHEN "0000" => Audio_reg_right <= "0000000000" & Audio_in_right_v(23 downto 10);
                        Audio_reg_left <= "0000000000" & Audio_in_left_v(23 downto 10);
                  
    WHEN "0001" => Audio_reg_right <= "000000000" & Audio_in_right_v(23 downto 9);
                       Audio_reg_left  <= "000000000" & Audio_in_left_v(23 downto 9);
                   
    WHEN "0010" => Audio_reg_right <= "00000000" & Audio_in_right_v(23 downto 8);
                        Audio_reg_left <= "00000000" & Audio_in_left_v(23 downto 8);
                   
    WHEN "0011" => Audio_reg_right <= "0000000" & Audio_in_right_v(23 downto 7);
                      Audio_reg_left <= "0000000" & Audio_in_left_v(23 downto 7);   
                  
    WHEN "0100" => Audio_reg_right <= "000000" & Audio_in_right_v(23 downto 6);
                      Audio_reg_left <= "000000" & Audio_in_left_v(23 downto 6);
                   
    WHEN "0101" => Audio_reg_right <= "00000" & Audio_in_right_v(23 downto 5);
                      Audio_reg_left <= "00000" & Audio_in_left_v(23 downto 5); 
                    
    WHEN "0110" => Audio_reg_right <= "0000" & Audio_in_right_v(23 downto 4);
                     Audio_reg_left <= "0000" & Audio_in_left_v(23 downto 4);
                    
    WHEN "0111" => audio_out_right <= "000" & Audio_in_right_v(23 downto 3);
                      Audio_reg_left <= "000" & Audio_in_left_v(23 downto 3);
                    
    WHEN "1000" => Audio_reg_right <= "00" & Audio_in_right_v(23 downto 2);
                       Audio_reg_left <= "00" & Audio_in_left_v(23 downto 2);
                    
    WHEN "1001" => Audio_reg_right <= "0" & Audio_in_right_v(23 downto 1);
                      Audio_reg_left <= "0" & Audio_in_left_v(23 downto 1);
                    
    WHEN "1010" => Audio_reg_right <= Audio_in_right_v(23 downto 0);
                      Audio_reg_left <= Audio_in_left_v(23 downto 0);
end case;
Audio_out_left_v <= Audio_reg_left;
Audio_out_right_v <= Audio_reg_right;
end if;
end process;

process(fpga_clk)
begin
  if volume = "11" then
    if volume_buff < 9 then
      volume_buff <= volume_buff +1;
    end if;
  elsif volume = "01" then
    if volume_buff > 0 then
    volume_buff <= volume_buff -1;
    end if;
  end if;
end process;
volume_to_vga <= volume_buff;
END ARCHITECTURE arch;

